//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_COMPORT_H__
#define __ELASTOS_COMPORT_H__

#define COMPORT_AVAILABLE(comPort) \
    (ComPort1 == (comPort) || ComPort2 == (comPort))

#define COMPORT_BASE(comPort) \
    ((ComPort1 == (comPort))? ComPort1_Base : ComPort2_Base)

enum {
    ComPort1_Base                   = 0xBFD003F8,
    ComPort2_Base                   = 0xBFD002f8,
};

// UART registers' port
#define COMPORT_DAT(base)           ((base) + 0)
#define COMPORT_DLLB(base)          ((base) + 0)
#define COMPORT_IER(base)           ((base) + 1)
#define COMPORT_DLHB(base)          ((base) + 1)
#define COMPORT_IIR(base)           ((base) + 2)
#define COMPORT_FCR(base)           ((base) + 2)
#define COMPORT_LCR(base)           ((base) + 3)
#define COMPORT_MCR(base)           ((base) + 4)
#define COMPORT_LSR(base)           ((base) + 5)
#define COMPORT_MSR(base)           ((base) + 6)
#define COMPORT_SR(base)            ((base) + 7)

#define COMPORT_CLOCKRATE           (115200)

// Interrupt Enable Register (IER)
#define IER_ERXINT      0x01    // Enable Received Data Available Interrupt
#define IER_ETXEINT     0x02    // Enable Transmitter Holding Register
                                //      Empty Interrupt
#define IER_ELSINT      0x04    // Enable Receiver Line Status Interrupt
#define IER_EMSINT      0x08    // Enable Modem Status Interrupt
#define IER_ESM         0x10    // Enables Sleep Mode (16750)
#define IER_ELPM        0x20    // Enables Low Power Mode (16750)

// Interrupt Identification Register (IIR)
#define IIR_NIP         0x01    // No Interrupt Pending
#define IIR_MSINT       0x00    // Modem Status Interrupt
#define IIR_TXINT       0x02    // Transmitter Holding Register Empty Interrupt
#define IIR_RXINT       0x04    // Received Data Available Interrupt
#define IIR_LSINT       0x06    // Receiver Line Status Interrupt
#define IIR_RXTINT      0x0c    // 16550 Time-out Interrupt Pending
#define IIR_64FE        0x20    // 64 Byte Fifo Enabled (16750 only)
#define IIR_NF          0x00    // No FIFO
#define IIR_FEU         0x80    // FIFO Enabled but Unusable
#define IIR_FE          0xc0    // FIFO Enabled

#define IIR_INTBITMASK  0x0f    // Interrupt Bit Mask

// First In / First Out Control Register (FCR)
#define FCR_EF          0x01    // Enable FIFO's
#define FCR_CRXF        0x02    // Clear Receive FIFO
#define FCR_CTXF        0x04    // Clear Transmit FIFO
#define FCR_DMA         0x08    // DMA Mode Select
#define FCR_E64F        0x20    // Enable 64 Byte FIFO (16750 only)
#define FCR_ITL_1       0x00    // Interrupt Trigger Level 1 Byte
#define FCR_ITL_4       0x40    // Interrupt Trigger Level 4 Bytes
#define FCR_ITL_8       0x80    // Interrupt Trigger Level 8 Bytes
#define FCR_ITL_14      0xc0    // Interrupt Trigger Level 14 Bytes

// Line Control Register (LCR)
#define LCR_WL_5        0x00    // Word Length 5 Bits
#define LCR_WL_6        0x01    // Word Length 6 Bits
#define LCR_WL_7        0x02    // Word Length 7 Bits
#define LCR_WL_8        0x03    // Word Length 8 Bits
#define LCR_SB_1        0x00    // 1 Stop Bit
#define LCR_SB_1_5      0x04    // 1.5 Stop Bit
#define LCR_SB_2        LCR_SB_1_5  // 2 Stop Bit
#define LCR_NP          0x00    // No Parity
#define LCR_OP          0x08    // Odd Parity
#define LCR_EP          0x18    // Even Parity
#define LCR_HP          0x28    // High Parity (Sticky)
#define LCR_LP          0x38    // Low Parity (Sticky)
#define LCR_SBE         0x40    // Set Break Enable
#define LCR_DLAB        0x80    // Divisor Latch Access Bit

// Modem Control Register (MCR)
#define MCR_DTR         0x01    // Force Data Terminal Ready
#define MCR_RTS         0x02    // Force Request to Send
#define MCR_AO1         0x04    // Aux Output 1
#define MCR_AO2         0x08    // Aux Output 2
#define MCR_LBM         0x10    // LoopBack Mode
#define MCR_ACE         0x20    // Autoflow Control Enabled (16750 only)

// Line Status Register (LSR)
#define LSR_DR          0x01    // Data Ready
#define LSR_OERR        0x02    // Overrun Error
#define LSR_PERR        0x04    // Parity Error
#define LSR_FERR        0x08    // Framing Error
#define LSR_BI          0x10    // Break Interrupt
#define LSR_ETHR        0x20    // Empty Transmitter Holding Register
#define LSR_EDHR        0x40    // Empty Data Holding Registers
#define LSR_ERF         0x80    // Error in Received FIFO
#define LSR_ERRS        (LSR_OERR | LSR_PERR | LSR_FERR) // Error mask

// Modem Status Register (MSR)
#define MSR_DCTS        0x01    // Delta Clear to Send
#define MSR_DDSR        0x02    // Delta Data Set Ready
#define MSR_TERI        0x04    // Trailing Edge Ring Indicator
#define MSR_DDCR        0x08    // Delta Data Carrier Detect
#define MSR_CTS         0x10    // Clear To Send
#define MSR_DSR         0x20    // Data Set Ready
#define MSR_RI          0x40    // Ring Indicator
#define MSR_CD          0x80    // Carrier Detect
#define MSR_MCSMASK     0xf0    // Modem Current Status Mask

#endif // __ELASTOS_COMPORT_H__
